1. Field of the Invention
This invention relates to an ultraviolet erasable nonvolatile semiconductor device having a floating gate and a control gate, in which the stored data is erasable by irradiation of ultraviolet rays.
2. Description of the Related Art
There is known an ultraviolet erasable nonvolatile semiconductor device having a floating gate, a control gate, and an insulating layer interlayered between these gates. This type of the memory device often employs a three-layered insulating layer for that gate insulating layer interlayered between the floating gate and the control gate. The three-layered gate insulating layer consists of a silicon oxide layer, a silicon nitride layer, and silicon oxide layer. Use of the gate insulating layer of the three-layered structure improves a breakdown voltage between the floating gate and the control gate, and additionally improves a defect density of the insulating layer per se. The oxide silicon layer as the top layer of the three-layered insulating layer is usually formed by oxidizing the silicon nitride layer by burning oxidization process. When an EPROM using memory cells whose gate insulating layer laid between the floating gate and the control gate utilized a three-layered structure, is compared with that using the memory cells whose gate insulating layer consists of only a silicon oxide layer, the former is inferior to the latter in the data erase characteristic. For details of this, reference is made to "Reliable CVD Interpoly Dielectrics for Advanced E and E.sup.2 PROM" in technical digest paper, page 16, in 1985 VLSI symposium. This paper describes that when the memory cell whose interlayered insulating layer utilizes a three-layered structure needs a long data erase time, approximately three times the data erase time of the memory cell whose interlayered insulating layer is a single silicon oxide layer formed by normal thermal oxidization process.